View IS31AP4833_4624259.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

IS31AP4833 integrated silicon solution, inc. ? www.issi.com 1 rev. a, 07/22/2012 treble and bass control with 3d enhancement audio power driver august 2012 general description the IS31AP4833 is a treble and bass control with 3d enhancement audio power driver. the IS31AP4833 provides tone (bass and treble) controls and volume control as well as a stereo audio power amplifier capable of delivering 2.8w into 4 ? with less than 10% thd with a 5v supply. the IS31AP4833 uses flexible i2c control interface for multiple application requirements. it also features 3d sound circuitry which can be externally adjusted via a simple rc network. the IS31AP4833 features a 13 steps tone control (-12db ~ +12db, 2db/step) and a 29 steps volume control (mute, -42db ~ +12db, 2db/step) for the headphone and stereo outputs. the volume and tone are controlled through an i2c compatible interface. the IS31AP4833 can get independent volume control for two channels. IS31AP4833 is available in qfn-36(4mm 4mm) and tqfp-48(7mm 7mm) package. it operates from 3.0v to 5.5v over the temperature range of -40c to +85c. features ? 3.0v to 5.5v supply ? mute control ? treble and bass control ? independent volume control for two channels ? stereo input mux ? i2c control interface ? 3d enhancement ? thermal shutdown protection ? click-and-pop suppression ? qfn-36(4mm 4mm) and tqfp-48(7mm 7mm) package applications ? cell phones, pda, mp4, pmp ? portable and desktop computers ? desktops audio system ? multimedia monitors typical application circuit figure 1 typical application circuit
IS31AP4833 integrated silicon solution, inc. ? www.issi.com 2 rev. a, 07/22/2012 pin configuration package pin configuration (top view) qfn-36 tqfp-48 1 2 3 4 42 29 33 25 26 41 40 39 13 15 16 19 5 20 27 38 6 21 28 nc hp 3d_en rst bypass nc scl tor outr+ tir lor lol nc til outl+ nc inl1 inl+ inr3 inr+ inr- gnd inl- 7 14 sdb vcc 30 lir 43 inr2 37 31 32 8nc nc 9 outl- 17 18 3dn 3dp 44 45 10 lil 11 tol 12 sda 22 23 24 gnd 36 inr1 34 35 outr- vcc nc 46 47 inl3 48 inl2 gnd nc nc nc nc gnd
IS31AP4833 integrated silicon solution, inc. ? www.issi.com 3 rev. a, 07/22/2012 pin description no. pin description qfn-36 tqfp-48 1 1 inl1 left channel single-ended input1. 2 3 lol left channel tone control loop out. 3 4 til left channel tone control in. 4 5 outl+ positive output of left channel. 5, 23 7,30 vcc power supply. 6 9 outl- negative output of left channel. 7 10 lil left channel tone control loop in. 8 11 tol left channel tone control out. 9 12 sda i2c serial data. 10 14 sdb it will into shutdown mode when pull low. 11 15 bypass bypass capacitor which provides the common mode voltage. 12 2,6,8,13,16,24, 29,31,35,38,47 nc no connection. 13 17 rst reset chip logic and states. active low. 14,32 18,19,42,43 gnd ground. 15 20 hp detect hp insert or not. 16 21 3d_en it will into 3d enhance mode when pull high. 17 22 3dn negative channel 3d input. 18 23 3dp positive channel 3d input. 19 25 scl i2c serial clock. 20 26 tor right channel tone control out. 21 27 lir right channel tone control loop in. 22 28 outr- negative output of right channel. 24 32 outr+ positive output of right channel. 25 33 tir right channel tone control in. 26 34 lor right channel tone control loop out. 27 36 inr1 right channel single-ended input1. 28 37 inr2 right channel single-ended input2. 29 39 inr3 right channel single-ended input3. 30 40 inr+ right channel positive differential input. 31 41 inr- right channel negative differential input. 33 44 inl- left channel negative differential input. 34 45 inl+ left channel positive differential input. 35 46 inl3 left channel single-ended input3. 36 48 inl2 left channel single-ended input2. thermal pad connect to gnd.
IS31AP4833 integrated silicon solution, inc. ? www.issi.com 4 rev. a, 07/22/2012 ordering information industrial range: -40c to +85c order part no. package qty IS31AP4833-qfls2-tr IS31AP4833-tqls2 qfn-36, lead-free tqfp-48, lead-free 2500/reel 250/tray copyright ? ? ? 2012 ? integrated ? silicon ? solution, ? inc. ? all ? rights ? reserved. ? issi ? reserves ? the ? right ? to ? make ? changes ? to ? this ? specification ? and ? its ? products ? at ? any ? time ? without ? notice. ? issi ? assumes ? no ? liability ? arising ? out ? of ? the ? application ? or ? use ? of ? any ? information, ? products ? or ? services ? described ? herein. ? customers ? are ? advised ? to ? obtain ? the ? latest ? version ? of ? this ? device ? specification ? before ? relying ? on ? any ? published ? information ? and ? before ? placing ? orders ? for ? products. ? integrated ? silicon ? solution, ? inc. ? does ? not ? recommend ? the ? use ? of ? any ? of ? its ? products ? in ? life ? support ? applications ? where ? the ? failure ? or ? malfunction ? of ? the ? product ? can ? reasonably ? be ? expected ? to ? cause ? failure ? of ? the ? life ? support ? system ? or ? to ? significantly ? affect ? its ? safety ? or ? effectiveness. ? products ? are ? not ? authorized ? for ? use ? in ? such ? applications ? unless ? integrated ? silicon ? solution, ? inc. ? receives ? written ? assurance ? to ? its ? satisfaction, ? that: ? a.) ? the ? risk ? of ? injury ? or ? damage ? has ? been ? minimized; ? b.) ? the ? user ? assume ? all ? such ? risks; ? and ? c.) ? potential ? liability ? of ? integrated ? silicon ? solution, ? inc ? is ? adequately ? protected ? under ? the ? circumstances
IS31AP4833 integrated silicon solution, inc. ? www.issi.com 5 rev. a, 07/22/2012 absolute maximum ratings supply voltage, v cc - 0.3v ~ +6.0v voltage at any input pin - 0.3v ~ v cc +0.3v maximum junction temperature, t jmax 150c storage temperature range, t stg - 65c ~ +150c operating temperature range, t a - 40c ~ +85c note: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of th e specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics t a = 25c, unless otherwise noted. typical value are t a = 25c, v cc = 3.6v. symbol parameter condition min. typ. max. unit v cc supply voltage 3.0 5.5 v i sd shutdown current v sdb = 0v 1 a v sdb = v cc , software shutdown 1 i cc quiescent power supply current v in = 0v, i o = 0a, v hp = 0v, no load 6 ma v in = 0v, i o = 0a, v hp = 5v, no load 4 v ih_hp hp input high-voltage v cc = 5.0v 4.1 v v cc = 3.0v 2.3 v il_hp hp input low-voltage v cc = 5.0v 3.4 v v cc = 3.0v 1.54 v ih input high-voltage 1.4 v v il input low-voltage 0.4 v ac characteristics (note 1) t a = 25c, v cc = 5.0v, unless otherwise noted. symbol parameter condition min. typ. max. unit po output power thd+n = 10%, f = 1khz, r l = 4 ? , speaker 2.80 w thd+n = 1%, f = 1khz, r l = 4 ? , speaker 2.20 thd+n = 10%, f = 1khz, r l = 8 ? , speaker 1.75 thd+n = 1%, f = 1khz, r l = 8 ? , speaker 1.45 thd+n = 10%, f = 1khz, r l = 32 ? , headphone 0.11 thd+n = 1%, f = 1khz, r l = 32 ? , headphone 0.091 thd+n total harmonic distortion plus noise p o = 1.5w, f = 1khz, r l = 4 ? , speaker 0.069 % p o = 0.9w, f = 1khz, r l = 8 ? , speaker 0.046 p o = 75mw, f = 1khz, r l = 32 ? , headphone 0.022 t wu wake-up time from shutdown 130 ms psrr power supply rejection ratio v cc = 3.0v, f = 217hz, r l = 8 ? k, speaker -67 db v no noise v cc = 3.0v~5.0v, v in = 0v, r l = 4 ? , speaker 60 v
IS31AP4833 integrated silicon solution, inc. ? www.issi.com 6 rev. a, 07/22/2012 digital input switching characteristics (note 1) symbol parameter condition min. typ. max. unit f scl serial-clock frequency 400 khz t buf bus free time between a stop and a start condition 1.3 s t hd, sta hold time (repeated) start condition 0.6 s t su, sta repeated start condition setup time 0.6 s t su, sto stop condition setup time 0.6 s t hd, dat data hold time 0.9 s t su, dat data setup time 100 ns t low scl clock low period 1.3 s t high scl clock high period 0.7 s t r rise time of both sda and scl signals, receiving (note 2) 20+0.1cb 300 ns t f fall time of both sda and scl signals, receiving (note 2) 20+0.1cb 300 ns note 1: guaranteed by design. note 2: cb = total capacitance of one bus line in pf. i sink 6ma. t r and t f measured between 0.3 v cc and 0.7 v cc .
IS31AP4833 integrated silicon solution, inc. ? www.issi.com 7 rev. a, 07/22/2012 typical performance characteristics thd+n(%) output power(w) 20 0.1 0.2 0.5 1 2 5 10 10m 3 20m 50m 100m 200m 500m 12 4 0.05 r l = 4 ? f = 1khz v cc = 5.0v v cc = 3.0v figure 2 thd+n vs. output power thd+n(%) output power(w) 20 0.1 0.2 0.5 1 2 5 10 10m 20m 100m 200m 500m 12 0.05 r l = 8 ? f = 1khz v cc = 5.0v v cc = 3.0v 50m 0.02 0.01 figure 4 thd+n vs. output power thd+n(%) output power(w) 20 0.1 0.2 0.5 1 2 5 10 1m 2m 5m 10m 20m 50m 100m 200m 0.05 0.02 0.01 r l = 32 ? f = 1khz v cc = 3.0v v cc = 5.0v figure 6 thd+n vs. output power 0.01 0.02 0.05 0.1 0.2 1 2 10 thd+n(%) 20 20k 50 100 200 500 1k 2k 5k 10k frequency(h z) 20 5 0.5 r l = 4 ? v cc = 5.0v p o = 1.5w v cc = 3.0v p o = 450mw figure 3 thd+n vs. frequency 0.01 0.02 0.05 0.1 0.2 1 2 10 thd+n(%) 20 20k 50 100 200 500 1k 2k 5k 10k frequency(hz) 20 5 0.5 r l = 8 ? v cc = 5.0v p o = 900mw v cc = 3.0v p o = 270mw figure 5 thd+n vs. frequency 0.01 0.02 0.05 0.1 0.2 1 2 10 thd+n(%) 20 20k 50 100 200 500 1k 2k 5k 10k frequency(hz) 20 5 0.5 r l = 32 ? v cc = 5.0v p o = 75mw v cc = 3.0v p o = 25mw figure 7 thd+n vs. frequency
IS31AP4833 integrated silicon solution, inc. ? www.issi.com 8 rev. a, 07/22/2012 output voltage(v) 20 20k 50 100 200 500 1k 2k 5k 10k frequency(hz) 10u 200u 20u 30u 50u 70u 100u v cc = 3.0v, 5.0v r l = 4 ? figure 8 noise vs. frequency power supply(v) output power(w) 0 0.5 1 1.5 2 2.5 3 3.5 3 3.5 4 4.5 5 5.5 r l = 4 ? f = 1khz thd+n = 10% thd+n = 1% figure 10 output power vs. power supply output level(db) 20 20k 50 100 200 500 1k 2k 5k 10k frequency(hz) -15 +20 -10 -5 +0 +5 +10 +15 v cc = 5.0v r l = 8 ? figure 12 bass and treble response vs. frequency psrr(db) 20 20k 50 100 200 500 1k 2k 5k 10k frequency(h z) -120 +0 -100 -80 -60 -40 -20 r l = 8 ? v cc = 3.0v v cc = 5.0v figure 9 psrr vs. frequency power supply(v) output power(w) 0 0.5 1 1.5 2 2.5 33.5 44.5 55.5 r l = 8 ? f = 1khz thd+n = 1% thd+n = 10% figure 11 output power vs. power supply
IS31AP4833 integrated silicon solution, inc. ? www.issi.com 9 rev. a, 07/22/2012 functional block diagram
IS31AP4833 integrated silicon solution, inc. ? www.issi.com 10 rev. a, 07/22/2012 detailed description i2c interface the IS31AP4833 uses a serial bus, which conforms to the i2c protocol, to control the chip?s functions with two wires: scl and sda. the IS31AP4833?s slave address is ?1000 0000?. it only supports write operations. the scl line is uni-directional. the sda line is bi-directional (open-collector) with a pull-up resistor (typically 4.7k ? ). the maximum clock frequency specified by the i2c standard is 400khz. in this discussion, the master is the microcontroller and the slave is the IS31AP4833. the timing diagram for the i2c is shown in figure 13. the sda is latched in on the stable high level of the scl . when there is no interface activity, the sda line should be held high. the ?start? signal is generated by lowering the sda signal while the scl signal is high. the start signal will alert all devices attached to the i2c bus to check the incoming address against their own chip address. the 8-bit chip address is sent next, most significant bit first. each address bit must be stable while the scl level is high. after the last bit of the chip address is sent, the master checks for the IS31AP4833?s acknowledge. the master releases the sda line high (through a pull-up resistor). then the master sends an scl pulse. if the IS31AP4833 has received the address correctly, then it holds the sda line low during the scl pulse. if the sda line is not low, then the master should send a ?stop? signal (discussed later) and abort the transfer. following acknowledge of IS31AP4833, the register address byte is sent, most significant bit first. IS31AP4833 must generate another acknowledge indicating that the register address has been received. then 8-bit of data byte are sent next, most significant bit first. each data bit should be valid while the scl level is stable high. after the data byte is sent, the IS31AP4833 must generate another acknowledge to indicate that the data was received. the ?stop? signal ends the transfer. to signal ?stop?, the sda signal goes high while the scl signal is high. figure 13 interface timing figure 14 bit transfer figure 15 writing to IS31AP4833
IS31AP4833 integrated silicon solution, inc. ? www.issi.com 11 rev. a, 07/22/2012 register description table 1 byte function address bit data bit function table default d7:d5 d4 d3 d2 d1 d0 000 - igs audio input gain control 2 0000 0110 001 - bgs bass control 3 0010 0110 010 - tgs treble control 4 0100 0110 011 lvs left channel gain control 5 0111 0000 100 rvs right channel gain control 6 1001 0000 101 - ims audio input mux control 7 1010 0000 111 me - 3de se ssd operating mode control 8 1110 0000 table 2 audio input gain control byte bit address bit data bit d7:d5 d4:d3 d2:d0 name 000 - igs default 000 00 110 configure the input gain. igs input gain select input resistor 000 -15db 85k ? 001 -12db 80k ? 010 -9db 74k ? 011 -6db 67k ? 100 -3db 59k ? 101 +0db 50k ? 110 +3db 41k ? 111 +6db 33k ? table 3 bass control byte bit address bit data bit d7:d5 d4 d3:d0 name 001 - bgs default 001 0 0110 configure the bass gain. bgs bass gain select 0000 -12db 0001 -10db 0010 -8db 0011 -6db 0100 -4db 0101 -2db 0110 0db 0111 +2db 1000 +4db 1001 +6db 1010 +8db 1011 +10db 1100 +12db
IS31AP4833 integrated silicon solution, inc. ? www.issi.com 12 rev. a, 07/22/2012 table 4 treble control byte bit address bit data bit d7:d5 d4 d3:d0 name 010 - tgs default 010 0 0110 configure the treble gain. tgs treble gain select 0000 -12db 0001 -10db 0010 -8db 0011 -6db 0100 -4db 0101 -2db 0110 0db 0111 +2db 1000 +4db 1001 +6db 1010 +8db 1011 +10db 1100 +12db table 5 left channel gain control byte bit address bit data bit d7:d5 d4:d0 name 011 lvs default 011 10000 configure the left channel gain (see table 9). lvs left volume select 00000 mute 00001 -42db 00010 -40db 00011 -38db ? ? 10000 -12db ? ? 10110 +0db 10111 +2db ? ? 111xx +12db table 6 right channel gain control byte bit address bit data bit d7:d5 d4:d0 name 100 rvs default 100 10000 configure the right channel gain (see table 9). rvs right volume select 00000 mute 00001 -42db 00010 -40db 00011 -38db ? ? 10000 -12db ? ? 10110 +0db 10111 +2db ? ? 111xx +12db table 7 audio input mux control byte bit address bit data bit d7:d5 d4:d2 d1:d0 name 101 - ims default 101 000 00 single-ended or differential input selected. ims input mux select 00 single-ended input 1 01 single-ended input 2 10 single-ended input 3 11 differential input
IS31AP4833 integrated silicon solution, inc. ? www.issi.com 13 rev. a, 07/22/2012 table 8 operating mode control byte bit address bit data bit d7:d5 d4 d3 d2 d1 d0 name 111 me - 3de se ssd default 111 0 0 0 0 0 configure the operating mode for IS31AP4833. ssd shutdown enable 0 operating mode 1 shutdown mode se speaker enable 0 speaker enable 1 speaker disable 3de 3d enable 0 3d off 1 3d on me mute enable 0 mute disable 1 mute enable table 9 left/right channel gain control data gain data gain 00000 mute 01111 -14 00001 -42 10000 -12 00010 -40 10001 -10 00011 -38 10010 -8 00100 -36 10011 -6 00101 -34 10100 -4 00110 -32 10101 -2 00111 -30 10110 +0 01000 -28 10111 +2 01001 -26 11000 +4 01010 -24 11001 +6 01011 -22 11010 +8 01100 -20 11011 +10 01101 -18 111xx +12 01110 -16
IS31AP4833 integrated silicon solution, inc. ? www.issi.com 14 rev. a, 07/22/2012 application information 3d enhancement the IS31AP4833 has a 3d audio enhancement effect that helps improve the apparent stereo channel separation when, because of cabinet or equipment limitations, the left and right speakers are closer to each other than optimal. decreasing the resistor size will make the 3d effect more pronounced and decreasing the capacitor size will raise the cutoff frequency for the effect. a 68nf capacitor is used to reduce the effect at frequencies below 1khz. increasing the value of the capacitor will decrease the low cutoff frequency at which the stereo enhanced effect starts to occur as shown below d d c r d f 3 3 2 1 3 ? ? (1) for example, according to the figure 1, r 3d = 2.7k ? , c 3d = 68nf so, hz d f nf k 867 3 68 7 . 2 2 1 ? ? ? ? ? ? the 3d enhancement effect enabled by setting the 3de bit of the control byte ?111x xxxx?. when setting the 3de bit to ?1?, 3d enhancement enabled. when setting the 3de bit to ?0?, 3d enhancement disabled. pulling the 3d_en pin to high will enable the 3d enhancement either. set the 3de bit to ?1? or pull the 3d_en pin to high will enable the 3d enhancement. shutdown the 3d enhancement should set the 3de bit to ?0? and pull the 3d_en pin to low. tone control response bass and treble tone controls are included in the IS31AP4833. the tone controls use two external capacitors for each stereo channel (c 1l c 2l c 1r c 2r ). each has a corner frequency determined by the value of c 1 , c 2 and internal resistors in the feedback loop of the internal tone amplifier. with c = c 1 = c 2 , the treble turn-over frequency is nominally c k tt f ? ? ? ? 56 2 1 ? (2) and the bass turn-over frequency is nominally c k bt f ? ? ? ? 3 . 113 2 1 ? (3) for example, according to the figure 1, c 1 = c 2 = 2.2nf so, khz tt f nf k 3 . 1 2 . 2 56 2 1 ? ? ? ? ? ? hz bt f nf k 639 2 . 2 3 . 113 2 1 ? ? ? ? ? ? the bass and treble gain can be adjusted independently by the control byte ?010x xxxx? and ?001x xxxx? (table 3, 4). gain selection the left/right channel gain can be adjusted by the lvs bit of the control byte ?011x xxxx? and the rvs bit of the control byte ?100x xxxx? (table 5, 6). in the speaker mode the output gain is equaled to audio input gain(igs)+left/right channel gain(lvs/rvs)+6db. in the headphone mode the output gain is equaled to audio input gain(igs)+left/right channel gain(lvs/rvs). input capacitors (c in ) the input capacitors (c in ) and internal resistor (r in ) form a high-pass filter with the corner frequency, f c , determined in equation (4). in in c r c f ? 2 1 ? (4) the value of r in is following the audio input gain (see table 2). for example, in figure 1, c in = 220nf, the audio input gain is set to -3db, so the r in = 59k ? , then, hz c f nf k 12 220 59 2 1 ? ? ? ? ? ? the capacitors should have a tolerance of ? mute function by setting the lvs/rvs bit to ?00000? the left/right channel output will be mute independently (see table 5, 6). the me bit of the control byte ?111x xxxx? sets the mute function for left and right channels. when the me bit is set to ?1?, the left and right channels are both mute (see table 8). when the me bit is set to ?0?, the left and right channels will resume the volume before.
IS31AP4833 integrated silicon solution, inc. ? www.issi.com 15 rev. a, 07/22/2012 input signal selection IS31AP4833 can choose single-ended or differential signal for the input source. single-ended input 1, single-ended input 2, single-ended input 3 and differential input signal can be chosen by the ims bit of control byte ?101x xxxx?(see table 7). headphone mode IS31AP4833 can also be used to drive headphone. the ic will shut off the positive output if headphone plug-in has been detected. then the speaker will stop working and switch to the headphone mode. shutdown mode shutdown mode can either be used as a means of reducing power consumption. during shutdown mode all registers retain their data. software shutdown by setting ssd bit of the control byte ?111x xxxx? to ?1?, the IS31AP4833 will operate in software shutdown mode, wherein they consume only 1 a (typ.) current. hardware shutdown the chip enters hardware shutdown mode when the sdb pin is pulled low, wherein they consume only 1 a (typ.) current.
IS31AP4833 integrated silicon solution, inc. ? www.issi.com 16 rev. a, 07/22/2012 classification reflow profiles profile feature pb-free assembly preheat & soak temperature min (tsmin) temperature max (tsmax) time (tsmin to tsmax) (ts) 150c 200c 60-120 seconds average ramp-up rate (tsmax to tp) 3c/second max. liquidous temperature (tl) time at liquidous (tl) 217c 60-150 seconds peak package body temperature (tp)* max 260c time (tp)** within 5c of the specified classification temperature (tc) max 30 seconds average ramp-down rate (tp to tsmax) 6c/second max. time 25c to peak temperature 8 minutes max. figure 16 classification profile
IS31AP4833 integrated silicon solution, inc. ? www.issi.com 17 rev. a, 07/22/2012 packaging information qfn-36
IS31AP4833 integrated silicon solution, inc. ? www.issi.com 18 rev. a, 07/22/2012 tqfp-48 note: all dimensions in millimeters unless otherwise stated.

▲Up To Search▲

Price & Availability of IS31AP4833

	To Download IS31AP4833 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .